I. Field of the Invention
This invention relates generally to apparatus for measuring the jitter present at the transitions of a data stream, and more particularly to a jitter measurement circuit operative at gigabit per second data rates.
II. Discussion of the Prior Art
Many forms of digital communications rely upon serial data communications technology. Various modulation schemes have been devised to encode data into a bit-serial format, allowing it to be conveyed over a single electrical conductor or optical fiber. Such schemes must necessarily be self-clocking, i.e. the clock signal required to interpret the received bit-serial signal must, itself, be a discernable component of the signal. It is well known in the art to employ phased-locked loops or surface acoustic wave (SAW) devices to first recover the clock signal from the bit-serial data stream and then use the recovered clock signal to sample (strobe) the bit-serial signal to thereby determine the bit-by-bit information state of the received signal. Ideally, the recovered clock is adjusted in phase such that the active clock transition occurs midway between data transitions because it is here that the data has the highest probability of being stable and correct. In practical systems, there are many random and systematic perturbations which corrupt the signal to cause the timing relationship between the recovered clock and the transition of data to vary from the ideal. This variation is commonly known as "jitter".
A means to accurately measure jitter is important since this is one of the most important parameters for assessing the performance of a serial data link. Jitter determines the maximum signaling rate and error rate of the data link. A measurement of jitter may also be useful as a diagnostic tool to isolate existing faults in the data link or to sense degradation of the data link so that corrective maintenance for an impending failure can be accomplished. For maximum utility, particularly in the prediction of future error rate, the jitter measurement apparatus should fully characterize the distribution of jitter, i.e., the probability of error occurrence as a function of jitter magnitude. Hereafter this distribution will be referred to as the jitter profile.
The importance of this parameter has inspired many prior art schemes for jitter measurement apparatus. Typical prior art schemes involve a direct measurement of the jitter, i.e., the apparatus derives the jitter measurement by observing the actual time relationship between data transitions and clock transitions. Certain of these schemes combine a set of direct jitter measurements in a manner which generates information somewhat indicative of the jitter profile. For example, U.S. Pat. No. 3,771,059 to Jaquith Gould Butler teaches a circuit which produces a result indicative of both the peak and the RMS values of jitter. U.S. Pat. No. 5,220,581 to Frank D. Ferraiolo teaches a circuit which effectively sorts jitter measurements into bins to form a jitter histogram. The Ferraiolo technique provides more useful jitter information than Butler, but with the penalty of greater complexity. A low number of bins compromises the measurement accuracy while a large number of bins increases complexity and cost. Further, neither of these prior art schemes is useable for very high speed data links. Very high speed data links, such as the Network Systems Communications PS 32 Serial HIPPI interface board, operate near the propagation delay limits of the fastest logic circuitry currently available. The implementation of jitter measurement apparatus which subdivides the basic clock cycle in the manner taught by Ferraiolo would require logic circuits substantially faster than those used to implement the data link itself.